The present disclosure relates to a method of fabricating a semiconductor structure. More particularly, the present disclosure relates to a method for integrating multiple threshold voltage (Vt) devices on the same semiconductor chip.
Scaling bulk semiconductor technology beyond the 20 nm node faces formidable challenges, particularly for low power applications, due to the competing requirement of density, power and performance, and partially due to the increase in device variation and parasitic.
Extremely thin semiconductor-on-insulator (ETSOI) substrates have been recognized as a viable device architecture due to its superior short-channel control, inherent low device variability, and compatibility with current mainstream planar complementary metal oxide semiconductor (CMOS) processing. System-on-chip applications require various sets of transistors to achieve optimal tradeoff between power and performance. The lack of channel doping in ETSOI requires that multiple threshold voltage devices be achieved through techniques other than doping techniques.
In view of the above, there is a need for providing a method to achieve multiple threshold voltage devices (such as low, medium and high threshold voltage) on the same chip for applications with ETSOI and other semiconductor substrates. In particular, a method is needed that is simpler than the prior art and, which overcomes several challenges that are associated with current gate-first integration schemes.